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Last Name:
Anzu
Submitted by
on Dec 04 2014
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By:
Project:
http://www.ist.tugraz.at/staff/jobstmann...
From:
Martin Weiglhofer
Paper:
http://www.ist.tugraz.at/staff/jobstmann...
Summary
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Resource Type:
Code
License:
Other/Unknown
Language:
Perl
Data Format:
Description
Anzu synthesizes Verilog designs from specifications written in LTL (Linear Temporal Logic). Software last updated 13 April 2007.
Categorized in:
Applications
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Engineering Design
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Representation and Reasoning
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Automated Theorem Proving
|
Description Logic
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